Failure analysis methods or techniques are essential for developing, manufacturing, and qualifying ICs. These methods for locating and identifying defective portions of an IC can provide insight to manufacturing and processing defects and other device failure modes that must be corrected to improve the yield and reliability of ICs. One example of a manufacturing and processing defect that failure analysis methods may be applied to is open-circuit electrical conductors on ICs. Open-circuit electrical conductors may be defined as an electrically conducting pathway or means whose ability to transfer electrical signals from one part of the IC to another part of the IC has been compromised by one or more failure mechanisms. Examples of mechanisms that can produce open-circuit electrical conductors include stress voiding, electromigration, silicon migration in contact metallization, and design and processing defects. The large effort in the IC industry to understand the mechanisms by which open-circuit electrical conductors are produced is indicative of the serious and ubiquitous nature of this potential problem. In addition, the detection and localization of open-circuit electrical conductors in ICs becomes increasingly difficult as each succeeding generation of ICs becomes more complex with reduced feature sizes, reduced conductor line widths, and an increased number of interconnecting layers. As a result, there is a continuing need for the development of new and improved IC failure analysis methods and apparatus.
Many active and passive methods for IC failure analysis exist in the prior art as disclosed in the articles entitled, "IC Failure Analysis: Techniques and Tools for Quality and Reliability Improvement," by J. M. Soden and R. E. Anderson, Proceedings of the IEEE, Vol. 81, May 1993, pp. 703-715 and "Advanced Scanning Electron Microscopy Methods and Applications to Integrated Circuit Failure Analysis," by E. I. Cole, C. R. Bagnell Jr., B. G. Davies, A. M. Neacsu, W. V. Oxford, and R. H. Propst, Scanning Microscopy, Vol 2, No. 1, 1988, pp. 133-150.
Among the types of active methods for IC failure analysis are those that measure the response of the IC to an applied stimulus in the form of an electron beam. These active electron beam methods are preferably practiced with the use of a scanning electron microscope (SEM). The SEM provides a focused electron beam and means for scanning the electron beam over a portion of the IC. The SEM also allows the viewing of an image of the IC device structure by means of secondary electron emission. This image of the IC device structure may be combined with the image produced by the active methods above to aid in registering the locations of any defects in the IC. Examples of prior art active electron beam methods for IC failure analysis include capacitive coupling voltage contrast (CCVC), electron beam induced current (EB IC), biased resistive contrast imaging (BRCI), and charge-induced voltage alteration (CIVA).
The CCVC method is disclosed in an article entitled "Electron Beam Testing of Passivated Devices via Capacitive Coupling Voltage Contrast," by W. Reiners, K. D. Herrmann, and E. Kubalek, Scanning Microscopy, Vol. 2, No. 1, 1988, pp. 161-175. The CCVC method uses a changing voltage applied to a buried electrical conductor in the IC to produce a change in the secondary electron emission of an incident low-energy electron beam on the device surface of the IC. Since in the CCVC method, the primary electron beam does not need to penetrate through a passivation layer on the IC, a low electron beam energy may be used. The CCVC signal is the secondary electron emission from the IC device surface; and an analysis image is formed by measuring the spatial variation of this secondary electron emission signal over IC device surface. A limitation of the CCVC method is that secondary electron emission also occurs in the absence of any voltage applied to the IC; and thus the CCVC image includes features of the IC, resulting in a composite image that may complicate the search for defects in the IC. A further limitation of the CCVC method is that surface charging may prevent secondary electron emission from escaping the IC device surface, and this can degrade and obscure the CCVC image. Attempts have been made to overcome this surface charging limitation by recording the CCVC image very rapidly before the device surface charges to an extent that obscures the CCVC signal. However, this complicates the analysis method by requiring the use of high-speed image recording and processing apparatus. The CCVC method is applicable to measuring the logic levels of ICs and the voltage on internal test nodes of an IC.
The EBIC method is used to identify defects in the device layer of an IC by generating an electron-hole current in semiconductor junctions in the IC. A disadvantage of the EBIC method is that for ICs having a passivation layer, the primary electron beam must have sufficient energy to penetrate through the passivation layer to reach the semiconductor device layer in the IC. This electrical breakdown of the IC passivation layer requires a high-energy electron beam energy of up to 5,000 electron volts (eV) or more; and this high electron beam energy can result in radiation damage in metal-oxide-semiconductor (MOS) ICs.
The BRCI method generates a relative resistance map of the conductors on ICs by using the IC as a complex current divider. This method for the measurement of IC logic levels and conductor voltage levels in an IC is disclosed in a paper entitled "A New Technique for Imaging the Logic State of Passivated Conductors: Biased Resistive Contrast Imaging," by E. I. Cole Jr., presented at the 1990 International Reliability Physics Symposium, New Orleans, La., Mar. 27-29, 1990. The BRCI image is generated by monitoring small fluctuations in the power supply current of an IC as an electron beam is scanned over the IC device surface. A disadvantage of the BRCI method is that the electron beam energy is comparable to that of the EBIC method and can also produce radiation damage in MOS ICs.
A CIVA method employing a high-energy primary electron beam for analyzing open-circuit electrical conductors in passivated ICs (i.e. ICs having one or more passivation layers) is disclosed in a paper entitled "Rapid Localization of IC Open Conductors Using Charge-Induced Voltage Alteration," by E. I. Cole Jr. and R. E. Anderson presented at the 1992 International Reliability Physics Symposium, San Diego, Calif., Mar. 30-Apr. 2, 1992. The prior art CIVA method provides a fast, simple method for locating open-circuit electrical conductors, contact, and via defects in ICs that have been very difficult to identify with other analysis methods. The CIVA image is generated by monitoring the voltage shifts in a constant-current power supply as a high-energy (about 5,000 eV or more for a passivated IC) electron beam is scanned over a biased IC. As electrons from the high-energy electron beam are injected into nonfailing electrical conductors in the IC, the additional current, on the order of nanoamperes, is readily absorbed by the IC conductors (i.e. this additional current is conducted to other regions of the IC) and produces little change in the power supply voltage. However, when electrons from the high-energy electron beam are injected into an electrically floating (i.e. open-circuit) conductor, the voltage of the conductor becomes more negative. This abrupt change in voltage on the floating conductor due to exposure to the high-energy electron beam generates a temporary change in the voltage demand of the constant-current power supply that is biasing the IC. The temporary change in the power supply voltage, even for open-circuits with significant quantum mechanical tunneling current, may be about 100 millivolts or larger for a power supply voltage of about 5 volts.
The CIVA apparatus and method for IC failure analysis were developed to localize open-circuit electrical conductors on both passivated and depassivated ICs. An advantage of the CIVA method over the other active methods above is that the CIVA images are generated only from the electrically open circuit portion of a conductor; whereas many of the other methods including CCVC, EBIC, and BRCI show contrast variations due to features of the IC other than an electrically open-circuit electrical conductor. Thus a CIVA image may be initially generated showing only open-circuit electrical conductors in an IC. Then the CIVA apparatus may be adjusted to produce a CIVA image in combination with a secondary electron emission image of the same portion of the IC (generated by scanning the same electron beam either simultaneously with or separate from the CIVA image scan), and these images may be combined to form a composite image to further localize the defect within the IC.
Another advantage of the CIVA method is that it is capable of detecting open-circuit electrical conductors in which the open circuit is due to quantum mechanical electron tunneling. Such types of open circuits may arise from electromigration or stress voiding; and they are very difficult to detect by other failure analysis methods. Another advantage of the CIVA method is that it has a high selectivity that allows any open-circuit electrical interconnections on an entire IC to be identified and mapped in a single image.
A disadvantage of the prior art CIVA method is that the primary electron beam must have sufficient energy to penetrate through any passivation layers in the IC to the underlying open-circuit electrical conductors in order to generate a CIVA voltage signal. In the case of ICs having one or more passivation layers, this requirement necessitates the use of a primary electron beam with an energy sufficiently high to produce an electrical breakdown of the passivation layer and generate a conducting channel to the buried electrical conductors in the IC. This high electron beam energy of 5,000 to 10,000 electron volts or higher is disadvantageous since it results in radiation damage to the IC similar to that of other prior art high-energy electron beam analysis methods. Such radiation damage severely restricts the application of the prior art CIVA method and limits its use in IC production lines or for qualification of ICs.
It should be noted that in the case of unpassivated or depassivated ICs, there is no insulating passivation layer barrier to prevent the primary electron beam from reaching the open-circuit electrical conductors of the IC and hence a very low electron beam energy of, for example, 300 eV may be used to obtain a signal with the prior an CIVA method. In the practice and use of the prior an CIVA method, there was no teaching or suggestion that such low electron beam energies could be used for passivated ICs. For passivated ICs, it was instead taught that use of the prior art CIVA method required a primary electron beam having sufficient energy to cause an electrical breakdown in the passivation layers of the IC. The use of a low electron beam energy is known to be preferable to reduce the occurrence of radiation damage to the IC; but heretofore such a low energy beam was only known to be usable for unpassivated or depassivated ICs.
However, since ICs are preferably fabricated with at least one insulating passivating layer such as silicon dioxide or silicon nitride overlying the patterned electrical conductor and device layers, the use of a low electron beam energy with the prior art CIVA method required that the passivation layer by removed by etching or by other methods. This is disadvantageous for many reasons. Removing the passivation layer is time consuming. It may alter or otherwise affect other features of the IC. It may result in the generation of electrical shortcircuits in regions of overlapping electrical conductor layers. It may generate additional types of defects that may obscure or complicate the search for the original defects in the IC. And finally, it cannot be used on a production line where the goal is to perform failure analysis on completely processed IC die immediately prior to encapsulation to locate defective ICs while not damaging or otherwise affecting non-damaged ICs. Such depassivating methods are also unacceptable for inspection or qualification of completely processed IC die prior to incorporation into a multi-chip module or other type of package that may be assembled by a manufacturer or user of ICs.
Therefore, in the prior-an CIVA method, the preferred method of usage heretofore has been to leave the passivation layer intact and to increase the primary electron beam energy until an electrical breakdown of the insulating dielectric passivation layer occurs. This electrical breakdown allows the electron beam to penetrate from the device surface to the open-circuit electrical conductors of the IC forming a conducting channel and allowing the generation of a CIVA voltage signal. This high-energy method of usage of the prior art CIVA method (designated herein as high-energy CIVA) was known to result in some radiation damage to the IC; but no other method of usage was known heretofore for analysis of passivated ICs using the CIVA method. As a result, the prior-art high-energy CIVA apparatus and method has been heretofore limited primarily to failure analysis of defective passivated ICs with no possibility for wide-scale production line usage or for qualification.
Electron beam induced damage to passivated MOS ICs is discussed in an article entitled "Electron Beam Induced Damage on Passivated Metal Oxide Semiconductor Devices," by S. Gorlich and E. Kubalek, Scanning Electron Microscopy, Vol. I, 1985, pp. 87-95. Electron beam induced damage to ICs is more severe for MOS ICs than for bipolar ICs due to a penetration of the primary electrons into the deep-lying gate oxide. Studies of the influence of non-penetrating electron irradiation on the characteristics of passivated NMOS transistors, for example, show that significant damage can occur even when the primary electrons do not penetrate to the gate oxide. This damage is due to secondary x-rays generated by the primary electrons in the passivation layer of the IC, since these x-rays penetrate into the gate oxide. The primary damage mechanism in the gate oxide is the generation of electronhole pairs and the subsequent trapping of positive holes that then causes a change in the space charge. This change in the space charge results in a shift in the threshold voltage, V.sub.th, of the transistor. (The threshold voltage is defined as the transistor gate voltage required to generate a specified drain-to-source current at a specified drain-to-source voltage.) Furthermore, interface states at the gate oxide boundary may be affected. Both effects are responsible for altering the device parameters.
The severity of the radiation damage increases with the irradiation dosage (i.e. the time that a portion of the IC is exposed to an electron beam), with the primary electron beam energy, and with decreasing size of the gates of the transistors in the IC. Studies as reported in the above article by Gorlich et al for n-channel MOS transistors show that the same shift of the threshold voltage caused by irradiation using 10,000 eV electrons, is found at about 20 times higher doses of 5,000 eV electrons and 10,000 times higher doses of 1,000 eV electrons. And, since the severity of the radiation damage increases with a decreasing size of the gates of the transistors in the IC, the threshold voltage shift may be even larger for current and future generations of ICs with 1 micron or smaller gate sizes unless improved gate oxide materials with fewer intrinsic defect sites are developed to improve the radiation hardness. Thus, there is a substantial benefit and advantage to be gained by reducing the primary electron beam energy to about 1,000 eV or less since the radiation damage lessens over-proportionally with decreasing energy of the primary electron beam.
In the prior art high-energy CIVA method, it was known to use the lowest primary electron energy possible to build up the necessary conducting channel through the passivation layer to the electrical conductors to minimize the possibility of radiation damage to the IC under test. For typical IC passivation layers, an electron beam energy of greater than or equal to 5,000 eV is generally required to penetrate to the buried electrical conductors; and the electron beam energy must be increased for thicker passivation layers. For example, a 1 micron thick silicon dioxide (SiO.sub.2) passivation layer requires an electron beam energy of about 10,000 eV to form a conducting channel through the passivation layer.
In the use of the prior art high-energy CIVA method, primary electron beam energies of about 10,000 eV or more were often required for passivated complimentary metal-oxide-semiconductor (CMOS) ICs. For example, the above CIVA article by Cole Jr. et al discloses several examples of the use of the prior art high-energy CIVA method for passivated CMOS ICs. These examples include the use of a primary electron beam energy of 9,000 eV for a CMOS application-specific integrated circuit (ASIC) having a single metallization (conductor) layer; the use of a primary electron beam energy of 11,000 eV for a second single-level metal IC with a thicker passivation layer; and the use of a primary electron beam energy of 15,000 eV for a two-level metal (i.e. two conductor layer) 1-micron technology CMOS ICs with about 1 micron thick passivation layers. These examples show the high primary electron beam energies required by the prior art high-energy CIVA apparatus and method when used to analyze passivated ICs.
It was further known in the prior art high-energy CIVA method that exposure to the electron beam (i.e. the number of images that were acquired) should be limited to minimize radiation damage as is disclosed in the article by Gorlich et al. In the above CIVA article by Cole Jr. et al, measurements of IC damage due to exposure to a 5,000 eV primary electron beam are reported. These measurements for 3-micron gate n-channel transistors with a nine second per image scan rate show a nearly linear increase in the transistor threshold voltage with the number of images acquired. The threshold voltage shift is about 5% after 11 images are acquired and increases to nearly 50% for 50 images.
Therefore, although the prior an CIVA method has many desirable features and advantages for imaging open-circuit electrical conductors in ICs, its use for passivated ICs has heretofore been limited. What is needed is a CIVA method that operates at a low primary electron beam energy of about 1,000 eV or less. Such a low-energy CIVA method is disclosed in the present patent application.